library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity InputBlock is
  Port (PixelClk : in std_logic;
        RowClk : in std_logic;
        RowEN : in std_logic;
        VSync : in std_logic;
        Reset : in std_logic;
        Data : in std_logic_vector(15 downto 0);
        
        FPGAClk : in std_logic;
        Pixel : out std_logic_vector(15 downto 0);
        HSync : out std_logic;
        VertSync : out std_logic);
end InputBlock;
